It is well known to use sense amplifiers for evaluating and outputting the binary status of bit lines from a memory device. However, the design of such sense amps becomes critical in certain types of specialized memory such as cache memory. In memories which have a particularly small cycle time, the creation of precise timing signals is difficult. In a pre-charged type sense amp, the sense amp typically must be powered up for evaluation of the bit lines and must be powered down for pre-charging before the next evaluation. Capturing the data which the sense amp has evaluated, before the next pre-charge time, is difficult. Previous designs have solved this problem by providing a separate clock or enable signal to a latch. The timing for the latch-enable further complicates the overall timing design for the memory system.
In the context of ordinary static-type memory circuits, U.S. Pat. No. 4,612,631 issued Sep. 16, 1986 to Ochii discloses a memory circuit having sense amps and a data holding circuit which includes cross-coupled NAND gates. Because these gates are coupled directly to the bit lines, a relatively large load is placed on the sense amps, slowing their evaluation. In this type of circuit, the bit lines must be driven "full swing" (i.e., between the voltage normally taken as indicating a logical zero and the voltage, normally taken as indicating a logical one which will typically be Vcc-Vss, or about five volts). Driving the bit lines at full swing is particularly power-consumptive, especially where a large number of lines must be driven, as well as time consuming. Although this approach may be acceptable in some contexts, when a small-cycle-time memory circuit is necessary, the RC delay is unacceptable.
In the context of a dynamic random access memory, U.S. Pat. No. 4,758,995, issued Jul. 19, 1988 to Sato discloses first and second amplifying circuits which have a fully differential amplifier construction. Although the amplifier shown therein may be effective for some applications, when it is desired to minimize current consumption, for example, when a large number, such as 256, bit lines are to be sensed, an undesirably and unnecessarily large amount of power would be consumed.